Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.
In recent times, as information media such as computers have rapidly come into wide use, technology of a semiconductor device has been rapidly developed. To keep up with the rapid pace of development, it is necessary for the semiconductor device to be capable of operating at high speed and have high storage capacity. Therefore, technology of manufacturing the semiconductor device has been rapidly developed to improve the degree of integration, reliability, response speed, etc.
A process for manufacturing a semiconductor device includes a fabrication process that forms cells each having an integrated circuit by repeatedly forming a predetermined circuit pattern on a silicon substrate, and an assembly process that packages the substrate including the cells in units of a chip. An Electrical Die Sorting (EDS) process for testing electrical characteristics of cells formed over the substrate is performed between the fabrication process and the assembly process.
The above-mentioned EDS process may determine whether the cells formed over the substrate are good or defective. The EDS process is adapted to remove such defective cells prior to execution of the assembly process, such that efforts or costs consumed in the assembly process may be reduced. In addition, the defective cells may be detected in early stages and be reproduced through a repair process.
A more detailed description of the repair process is as follows.
In order to increase the production yield of semiconductor devices, a redundant cell is added to substitute for a defective device or circuit, and a fuse for coupling the redundant cell to the integrated circuit is also added to the manufacturing process of the semiconductor device. The repair process couples a defective cell detected by the test process to a redundant cell contained in the chip using the fuse, resulting in cell recovery.
A method for repairing the semiconductor device according to the related art will hereinafter be described in detail.
First of all, after a planarized interlayer insulation film is deposited over a fuse region of the semiconductor substrate, a plurality of fuse patterns is formed over the interlayer insulation film. Thereafter, an insulation film covering the fuse patterns is deposited over the resultant semiconductor substrate. Subsequently, repair-etching of some thickness of the insulation film is performed, so that a repair-trench that enables an insulation film having a predetermined thickness to remain in a blowing region (i.e., a fuse pattern) is formed.
Thereafter, established testing and repairing processes are sequentially performed, including a fuse blowing process that cuts a specific fuse by applying laser energy to the fuse region of the semiconductor substrate.
After a repair-trench that enables an insulation film having a predetermined thickness to remain on the fuse pattern is formed, a fuse blowing process is performed. In this case, provided that the insulation film remaining on the fuse pattern has a large thickness, when thermal energy is focused on the fuse during the fuse blowing and then reaches a threshold point, an upper explosion occurs in the fuse so that the fuse is blown. Provided that the insulation film has a large thickness, a crack occurs in a lower part prior to execution of the upper explosion, and a metal residue is generated in the crack, resulting in creation of a defective part. In contrast, provided that the insulation film remaining on the fuse pattern has a small thickness, thermal energy is better focused on the fuse. However, thermal energy is exposed and emitted to the air, so that defective or poor fuse blowing occurs.
In order to improve the defective fuse blowing, a metal bare fuse that need not adjust thickness of the remaining insulation film has been introduced. However, metal residue remains when the metal bare fuse is blown using a laser so that a defective fuse is generated. In addition, since an upper part and sidewalls of the metal bare fuse are exposed, oxygen or moisture is permeated into the exposed fuse in a subsequent process (i.e., a wafer packaging process), so that fuse volume expansion and fuse oxidation occur, resulting in a reduced production yield.
FIGS. 1(i) and 1(ii) are layout and cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention. In more detail, FIG. 1(i) is a layout of a semiconductor device, and FIG. 1(ii) is a cross-sectional view illustrating the semiconductor device.
Referring to FIG. 1, an interlayer insulation film 110 is formed over the semiconductor substrate 100. In this case, the interlayer insulation film 110 may include an oxide film.
Subsequently, a conductive layer (not shown) is formed over the interlayer insulation film 100. After a photoresist film is formed over the conductive layer, a photoresist pattern (not shown) is formed by the exposure and development process using a lower line mask. The conductive layer is etched using the photoresist pattern as a mask, so that a lower line 120 is formed.
Thereafter, a second interlayer insulation film 130 is formed over the lower line 120 and the exposed interlayer insulation film 110. The second interlayer insulation film 130 may include an oxide film.
After a photoresist film is formed over the second interlayer insulation film 130, a photoresist pattern (not shown) is formed using the exposure and development process with a contact plug mask. The second interlayer insulation film 130 is etched using the photoresist pattern as a mask until the lower line 120 is exposed, so that a contact plug region (not shown) is formed. After that, the conductive layer is buried in the contact plug region, so that the contact plug 140 is formed.
Subsequently, after a metal layer (not shown) is formed over the contact plug 140 and the second interlayer insulation film 130, a fuse pattern 150 coupled to the contact plug 140 is formed by etching the metal layer. In this case, the metal layer may include copper (Cu). The fuse pattern 150 may be formed in a pad or line shape.
After that, a third insulation film (not shown) is formed over the entire surface including the fuse pattern 150, and laser blowing 170 is performed in a predetermined region 160 of the fuse pattern 150. There arise many problems in the laser blowing 170; for example, a spot size or pitch of the laser may be larger than the fuse pattern 150 to be blown, or laser energy may be transferred even to the semiconductor substrate 100 due to a large wavelength or high intensity of the laser. Due to such laser blowing, damage of the semiconductor substrate 100 may occur as shown in the A part.